1. Field of the Invention
The invention relates in general to a manufacturing method of a flash memory, and more particular, to a manufacturing method of a flash memory with a square word line spacer.
2. Related Art of the Invention
The memory is literalized as a semiconductor device used to store information or data. As the functions of computer microprocessors become more and more powerful, and software programs become more and more massive, memory demand is becoming consequently higher and higher. To comply with the trends for fabricating memory with larger capacity and cheaper cost, the technique and process for memory fabrication is driven by the challenge of higher integration.
For example, the flash memory device allows the performance of multiple saving, reading and erasing operations. Plus the advantage that the data saved therein is retained even when the power is switched off, flash memory has become a nonvolatile memory device broadly applied in personal computer and electronic equipment.
The typical flash memory uses doped polysilicon for forming the floating gate and the control gate. The floating gate and the control gate are isolated from each other by a dielectric layer, while a tunnel oxide layer is formed between the floating gate and the substrate. While performing data write/erase operations, a bias is applied across the control gate and the source/drain region, so that electrons are injected into or pulled from the floating gate. While reading the data saved in the flash memory, a working voltage is applied to the control gate, such that the conducting status of the floating gate affects the on/off status of the underlying channel, the reference to determine the data value of xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d.
When performing data erase on flash memory, the relative voltage of the substrate, the drain (source) region or the control gate is raised. The electrons then tunnel through the tunneling oxide from the floating gate to the substrate or the drain (source) region, which is referred as the substrate erase or the drain (source) erase. Alternatively, the electrons tunnel through the dielectric layer to the control gate. However, in the erase operation of the data saved in the flash memory, the amount of electrons tunneling from the floating gate is difficult to control, often resulting in a positive charged floating gate by ejecting excessive amount of electrons. Such an effect is referred to as over-erase. When the over-erase becomes significant, the channel underneath the floating gate is continuously conducted even when the working voltage is not applied to the control gate to cause data error. To resolve the over-erase problem, the industry has developed tri-layered sub-gate high-density flash memory.
Referring to FIG. 1, a tunneling oxide layer 102, a floating gate 104 and a control gate 106 made of doped polysilicon are formed on a substrate 100. The floating gate 104 is formed underneath the control gate 106. After formation of the floating and control gates 104 and 106, dopant is implanted into the substrate 100 to form a source region 108. After forming the source region 108, a spacer 110 is formed on the sidewall of the floating and control gates 104 and 106. A polysilicon layer (not shown) is formed on the substrate 100, and an anisotropic etching process is performed to etch the polysilicon layer, such that a select gate 112 is formed on the sidewall of the spacer 110. The select gate 112 is used as the word line of the flash memory. A lightly doped region (LDD) 114 is then formed at one side of the select gate 112. A spacer 116 is formed on the select gate 112, and a drain region 118 is further formed in the substrate 100.
In the above fabrication process of the flash memory, as the select gate 112 is not formed in a square shape, the shape of the spacer 116 formed subsequently adversely affects the formation of the lightly doped region 114. Further, as the integration of the semiconductors increases, cobalt silicide is frequently formed on the select gate 112. If the shape of the spacer 116 is not optimized, contact between the contact window and cobalt silicide formed subsequently may seriously deteriorate the quality of devices and reduce the product yield. Therefore, to have the spacer of the gate structure formed with a square shape is crucial.
The present invention provides a manufacturing method of a flash memory allowing a select gate formed on the spacer of the stacked gate structure having a square shape, such that device performance is improved, and the product yield is enhanced.
The present invention further provides a simplified manufacturing method, by which a square-shaped spacer is formed on the sidewall of a stacked gate structure.
In the manufacturing method provided by the present invention, a substrate on which a gate structure is formed is provided. A source region is formed in the substrate at one side of the gate structure. A spacer is formed on the sidewall of the gate structure. A first conductive layer and a sacrificial layer are formed on the substrate, of which portions are removed using chemical mechanical polishing until the gate structure is exposed. A thermal oxidation process is performed to form a mask layer on the first conductive layer and the gate structure. The remaining sacrificial layer remaining on the first conductive layer is removed using the mask layer as a mask. The first conductive layer is etched into a square second conductive layer. The mask layer is removed. A lightly doped region is formed in the substrate at one side of the second conductive layer. A drain region is then formed in the substrate at the same side of the second conductive layer.
In the present invention, a conductive layer and a sacrificial layer are formed after formation of the gate structure, the source region and the spacer. Chemical mechanical polishing is applied to remove portions of the conductive layer and the sacrificial layer until the gate cap layer is exposed. The mask layer is then formed using thermal oxidation, and a wet etching step is performed to remove the sacrificial layer. The mask layer is then used as a mask to form the square select gate.
The present invention uses the mask layer as the etching mask directly, so that a photolithography process is not performed, allowing for a wider process window:The fabrication time and cost are thus reduced. Further, by the simplified process, a square select gate is formed to result in a good isolation effect for the spacer formed subsequently. The electrical contact between the contact window and the metal silicide can thus be avoided, while the device performance and product yield can be enhanced.
The present invention further provides a manufacturing method of a square spacer. A spacer on which a stacked structure is formed is provided. A conductive layer and a sacrificial layer are formed on the substrate. Portions of the conductive layer and the sacrificial layer are removed until the stacked structure is exposed. A mask layer is formed on the conductive layer and the stacked structure. The sacrificial layer on the conductive layer is then removed. Using the mask layer as a mask, the conductive layer is etched to form a square spacer.
After formation of the stacked structure, the conductive layer and the sacrificial layer are formed on the substrate. Chemical mechanical polishing is then performed to remove portions of the sacrificial layer and the conductive layer until the stacked structure is exposed. The thermal oxidation process is then performed to form the mask layer on the stacked structure and the conductive layer. A wet etching step is performed to remove the sacrificial layer. The mask layer is then used as a mask to etch the conductive layer, so as to form a square spacer.
The present invention uses the mask layer as the etching mask directly without performing photolithography, so that a spacer with a square shape can be easily formed with reduced cost and process time.